1. Field of the Invention
The present invention relates generally to clock generators, and specifically to duty-cycle adjustable high frequency clock generators.
2. Description of Related Art
Sinusoidal waveforms have traditionally been used in the clock line to control microwave devices in various microwave systems. Sinusoidal waveforms have also traditionally been used in high-data-rate optical communication applications, such as SERDES clocks and Non-Return-to-Zero (NRZ) to Return-to-Zero (RZ) signal conversion devices that can extend the transmission distance in fiber optical communication systems.
Adjustable duty cycle is one of the key features in clock circuitry in order to tune and yield the optimum system performance. As is understood in the art, the duty cycle of a signal is the percentage of time the signal is above or below a certain threshold. A duty-cycle adjustable signal at low RF frequency (i.e., below 15 MHz) can easily be accomplished using a rectangular-pulse clock signal that includes multiple (i.e., five or more) frequency harmonics. For low frequency applications, the rectangular-pulse clock has served as the basis for most commercial waveform generators.
However, the bandwidth that is required to generate and distribute a rectangular-pulse clock increases proportionally as the clock frequency increases. For example, FIG. 1 shows the frequency spectrum of a 10 GHz rectangular-pulse clock with 25% duty cycle. When the rectangular-pulse clock signal of FIG. 1 passes through band-limited amplifiers and a clock distribution network, the waveform of the rectangular-pulse clock signal becomes distorted, as shown in FIG. 2. FIG. 2 illustrates the distortion resulting from 10 GHz pulses passing through a 13-GHz band-limited distribution network. As a result, such rectangular-pulse clock signals cannot be used in high frequency (i.e., microwave and higher) applications.
Therefore, many applications have begun using a level-shifted sinusoidal waveform clock signal when the clock frequency is in the microwave range or higher. An example of a level-shifted sinusoidal waveform with 25% duty cycle and zero threshold voltage 20 is illustrated in FIG. 3. As can be seen in FIG. 3, the level-shifted sinusoidal waveform 50 is above zero volts, and therefore produces an xe2x80x9cONxe2x80x9d state 10 (illustrated by shaded areas) at the device-under-control (DUC), 25% of the time and below zero volts, and therefore produces an xe2x80x9cOFFxe2x80x9d state 15 (illustrated by non-shaded areas) at the DUC, 75% of the time. Therefore, the duty-cycle of the level-shifted sinusoidal waveform 50 shown in FIG. 3 is 25%.
Although using only a single sine wave as the clock signal removes the problem of distortion resulting from rectangular-pulse clock signals that include multiple frequency harmonics, several concerns are associated with the use of such level-shifted sinusoidal waveforms. First, there is a significant negative DC offset voltage produced by the level-shifted sinusoidal waveform. As can be seen from FIG. 3, the level-shifted sinusoidal waveform 50 has a DC offset voltage 25 of xe2x88x922.43 V. To accommodate the DC offset voltage 25 produced by the level-shifted sinusoidal waveform 50, DC coupled methods must be implemented on the distribution network (not shown), as well as at the input of the DUC (not shown). Further, when the duty-cycle changes, the DC level on the clock also changes, resulting in a drifting of the DC bias point on the DUC. Therefore, the DUC must also be designed to accommodate for the DC drifting effect, which can lead to a complicated and expensive circuit design for the DUC.
Secondly, the high negative voltage swing on the level-shifted sinusoidal clock signal results in a high transient reverse bias on the control port of the DUC. For example, as can be seen in FIG. 3, the reverse bias 30 of the level-shifted sinusoidal waveform 50 is approximately xe2x88x926.9 V. The transient reverse bias condition limits the application of the level-shifted sinusoidal clock to situations where the maximum reverse bias rating of the semiconductor device(s) at the control port of the DUC is greater than the reverse bias of the signal. As is understood in the art, exceeding the maximum reverse bias rating of a semiconductor device results in permanent damage to the device. For example, the maximum reverse bias rating of a microwave Schottky diode is less than xe2x88x925V. If a microwave Schottky diode, or other similar device, is present at the control port of the DUC, the level-shifted sinusoidal waveform 50 of the type shown in FIG. 3 cannot be used as the clock signal.
Third, the DC current produced by a level-shifted sinusoidal clock further limits the applications of the level-shifted sinusoidal clock signal to situations where the DC current produced by the level-shifted sinusoidal clock signal is able to be handled by the semiconductor device(s) at the control port of the DUC. As is understood in the art, to increase the cutoff frequency of a diode switch, the geometry of diode is reduced as the operating frequency increases. As a result, the higher the operating frequency, the lower the DC current handling capability. For example, if the DC current rating of a switch diode that is capable of operating at 40 GHz is approximately 2.5 mA, and there is approximately xe2x88x922 V DC on the clock line, the diode must have an 800-ohm average resistance or higher to be operated safely. However, an 800-ohm resistance is too high for use with a microwave switch. Therefore, the applications of level-shifted sinusoidal clock signal are limited by the large DC current produced by the level-shifted sinusoidal waveform.
Finally, a level-shifted sinusoidal waveform typically requires a large AC voltage swing. As shown in FIG. 3, the voltage swing of the level-shifted sinusoidal waveform 50 is approximately 8.86 Vpp. This large voltage swing translates into a large RF driver amplifier output power requirement and higher dissipated power. Therefore, what is needed is an adjustable duty cycle clock generator with low reverse bias and a zero DC level.
An adjustable duty-cycle clock generator that produces a clock signal with low reverse bias and zero DC level is achieved by power combining two sinusoidal waveforms with proper phase shift and magnitude control. The clock generator includes a fundamental sinusoidal waveform source, a second harmonic waveform source, a power combiner and phase shift and magnitude control devices. The duty-cycle adjustment is achieved by varying the magnitude ratio between the fundamental and the second harmonic waveforms.
Advantageously, the resulting clock signal has duty-cycle adjustable capability, zero DC level, a low reverse bias condition and a low RF requirement. As a result, the clock signal can be used effectively in various high frequency microwave/millimeter wave systems, as well as in high-data-rate optical communication systems. In addition, because the final waveform is a linear combination of two frequency components, the magnitude control and phase shift devices can further be used as pre-distortion devices to compensate for the frequency-response difference (i.e., phase variation) of the two frequency components through the clock distribution network. Using electronic and/or mechanical control devices for magnitude and phase control allows tuning at a system integration level to yield the optimum system operation point.